VIDEO ARCHIVE: 2011 Demo Sessions

ISSCC 2011 introduced a new event, the Industry Demonstration Session (IDS), that was held on Tuesday February 22. The IDS featured live demonstrations of selected ICs that were also presented by industry authors in regular paper sessions. The ICs included wireless communication, high-performance amplifiers, graphics processors, OLED microdisplays, energy harvesters, cellphones, and more. The IDS is intended to exemplify the real-life applications made possible by new ICs presented at ISSCC.

 

2011 IDS 7.6

7.6 A MIMO WiMAX SoC in 90nm CMOS for 300km/h Mobility

G. C. Chuang1, P-A. Ting1, J-Y. Hsu1, J-Y. Lai1, S-C. Lo1, Y-C. Hsiao1, T-D. Chiueh2
1ITRI, Hsinchu, Taiwan
2National Taiwan University, Taipei, Taiwan

 

This paper presents a 49mm2 WiMAX IEEE 802.16e baseband SoC implementing two 2×2 MIMO modes. The SoC integrates an ARM-926, flash and SDRAM controller, AES engine, USB 2.0, and a MAC structure with possible future extension to 802.16m/LTE. This chip can deliver data rates up to 30Mb/s in low mobility and 5Mb/s at 300km/h.

 

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2011 IDS 7.7

7.7 A 70Mb/s -100.5dBm Sensitivity 65nm LP MIMO chipset for WiMAX Portable Router

J-S. Pan, M-Y. Chao, E. Yeh, W-W. Yang, C-W. Hsueh, S. Liao, J-B. Lin, S-A. Yang, C-T. Liu, T-P. Lee, J-R. Chen, C-H. Chou, M. Chen, D-K. Juang, J-H. Yeh, C-W. Liao, P-H. Chen, K. Kao, C-H. Wu, W-T. Huang, S-H. Liao, C-H. Shih, C-H. Tung, Y-P. Lee
MediaTek, Hsinchu, Taiwan

 

This chipset consists of a dual-band 2×2 MIMO RF transceiver chip and a fully integrated WiMAX modem/router chip. The RF transceiver chip has low-power consumption of 364mW and up to 7dB sensitivity margin, and occupies 11.05mm2. The WiMAX modem/router chip is targeted for portable routers with power consumption of 632.7mW and up to 7dB sensitivity margin, and occupies 24.99mm2.

 

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2011 IDS 9.3

9.3 A 60GHz CMOS Phased-Array Transceiver Pair for Multi-Gb/s Wireless Communications

S. Emami, R. F. Wiser, E. Ali, M. G. Forbes, M. Q. Gordon, X. Guan, S. Lo, P. T. McElwee, J. Parker, J. R. Tani, J. M. Gilbert, C. H. Doan
SiBEAM, Sunnyvale, CA

 

A 60GHz phased-array transceiver pair is integrated in 65nm CMOS and packaged with an embedded antenna array, supporting the WirelessHD and draft IEEE 802.11ad standards. EVM of -19.2dB meets the spectral mask for 10m non-line-of-sight transmission of 3.8Gb/s over 16-QAM OFDM. Trade-offs between rate, range, and power consumption are described.

 

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2011 IDS 13.3

13.3 Filterless Integrated Class-D Audio Amplifier Achieving 0.0012% THD+N and 96dB PSRR When Supplying 1.2W

M. Teplechuk, T. Gribben, C. Amadi
Dialog Semiconductor, Edinburgh, United Kingdom

 

Filterless class-D audio amplifier with uniform pulse-width modulation architecture achieves 0.0012% THD+N delivering 1.2W into 8Ω with 93% power efficiency and 96dB PSRR. Amplifier is fabricated in a standard CMOS process and packaged in WLCSP with total chip area of 1.44mm2. Amplifier achieves 103dB SNR with quiescent current of 4mA and maximum output power of 3.1W.

 

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2011 IDS 13.8

13.8 A 3.3V-Supply 120mW Differential ADC Driver Amplifier in 0.18μm SiGe BiCMOS with 108dBc IM3 at 100MHz

G. F. Luff
Intersil, Harlow, United Kingdom

 

A fully differential ADC driver amplifier in 0.18μm NPN-only SiGe BiCMOS achieves 108 dBc IM3, delivering 2Vpp-diff composite two tone output at 100MHz into 200 ohms. Input noise is 0.85 nV/√Hz and 3dB bandwidth 2.2GHz. Consuming only 120mW from 3.3V supply, it has half the distortion at half the power of previous designs.

 

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2011 IDS 15.2

15.2 An 80Gb/s Dependable Communication SoC with PCI express I/F and 8 CPUs

S. Otani1, H. Kondo1, I. Nonomura2, A. Ikeya2, M. Uemura2, Y. Hayakawa1, T. Oshita1, S. Kaneko1, K. Asahina2, K. Arimoto1, S. Miura3, T. Hanawa3, T. Boku3, M. Sato3
1Renesas Electronics, Itami, Japan
2Renesas Electronics, Kodaira, Japan
3University of Tsukuba, Tsukuba, Japan

 

An 80Gb/s dependable communication 45nm SoC with four 4X PCIe Rev 2.0 ports and 8 CPUs acts as a communication link in an HPC cluster and can extend its role to the computing nodes in embedded systems. To achieve a highly dependable network, the communication SoC continuously monitors the network conditions and performs adaptive routing dynamically. The power consumption is 0.8W/port and consumes 51.5% less power than 4X InfiniBand.

 

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2011 IDS 15.4

15.4 A Low-Power Integrated x86-64 and Graphics Processor for Mobile Computing Devices

S. R. Gutta1, D. Foley2, A. Naini1, R. Wasmuth3, D. Cherepacha4
1AMD, Hyderabad, India
2AMD, Boxborough, MA
3AMD, Austin, TX
4AMD, Markham, Canada

 

Zacate is AMD's first generation Fusion SoC that combines x86 CPU and Radeon™ GPU on a single 40nm bulk CMOS die. The SoC uses an internal bus architecture and design echniques to optimize performance and memory bandwidth without compromising on power savings. ine-grain power gating, dynamic voltage/frequency scaling and enhanced display refresh are key nablers for low-power operation.

 

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2011 IDS 17.8

17.8 Bidirectional OLED Microdisplay: Combining Display and Image Sensor Functionality into a Monolithic CMOS chip

B. Richter, U. Vogel, R. Herold, K. Fehse, S. Brenner, L. Kroker, J. Baumgarten
Fraunhofer Institute for Photonic Microsystems, Dresden, Germany

 

This paper presents a bidirectional 320×240 monochrome OLED microdisplay with a nested 160×120 image sensor in 0.35μm CMOS for near-to-eye applications with embedded eye-tracking capabilities.

 

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2011 IDS 19.2

19.2 An 82μA/MHz Microcontroller with embedded FeRAM for Energy-Harvesting Applications

M. Zwerg1, A. Baumann1, R. Kuhn1, M. Arnold1, R. Nerlich1, M. Herzog1, R. Ledwa1, C. Sichert1, V. Rzehak1, P. Thanigai2, B. O. Eversmann1
1Texas Instruments, Freising, Germany
2Texas Instruments, Dallas, TX

 

A 16b MCU SoC with an embedded 16kB FeRAM reduces active current consumption to 82μA/MHz for code execution from the NVM. The performance of the memory subsystem is based on a 2k×72b FeRAM array with 55ns access time combined with a 2-way 2-line associative cache. A dedicated FeRAM power system with a fast fail detection ensures uninterrupted refresh cycles to the FeRAM.

 

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2011 IDS 21.1

21.1 A SAW-less GSM/GPRS/EDGE Receiver embedded in a 65nm CMOS SoC

I.S-C. Lu1, C-Y. Yu2, Y-H. Chen2, L-C. Cho2, C-H. E. Sun2, C-C. Tang2, G. Chien1
1MediaTek, San Jose, CA
2MediaTek, Hsinchu, Taiwan

 

A 65nm CMOS quad-band RX, embedded in a GSM SoC, complies with the ETSI standard without the need of external SAW filters. By using a Class-AB low noise amplifier and passive mixer with current-mode LPF, the RX achieves sensitivity of <-110 dBm, out-of-band P1dB of > +1dBm, and IIP2/IIP3 of >+44dBm/0dBm respectively. The transceiver consumes 58.9mA in the RX mode and occupies 4.94 mm2.

 

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2011 IDS 24.4

24.4 An EDGE/GSM Quad-Band CMOS Power Amplifier

W. Kim, K. Yang, J. Han, J. Chang, C-H. Lee
Samsung Electro-Mechanics, Atlanta, GA

 

A 0.18μm dual-mode quad-band CMOS PA with an integrated passive device is assembled in a 5x5mm2 QFN package. The linear PA for EDGE mode achieves an average output power of 28.5 dBm, a PAE of 22 %, an ACPR of -57dBc and an EVM-rms of 1.6% for GSM/EGSM bands. The PA as a switching amplifier performs an output power of 34.5dBm with a PAE of 55% for GSM application.

 

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2011 IDS 25.7

25.7 A 10Gb/s half-UI IIR-Tap Transmitter in 40nm CMOS

H. Cirit, M. J. Loinaz
Netlogic Microsystems, Santa Clara, CA

 

A transmit equalizer is designed for 10Gb/s serial communication and features half-UI, IIR and FIR taps. Both SFI transmitter waveform dispersion penalty (TWDPc for direct-attach copper cable) and data-dependent jitter (DDJ) specifications are met with a single transmitter configuration. The circuit, fabricated in 40nm CMOS, dissipates 125mW and occupies 0.22mm2.

 

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2011 IDS 26.3

26.3 A 2.4Ghz ULP OOK Single-chip Transceiver for Healthcare Applications

M. Vidojkovic1, X. Huang1, P. Harpe1, S. Rampu1, C. Zhou1, L. Huang1, K. Imamura2, B. Busze1, F. Bouwens1, M. Konijnenburg1, J. Santana1, A. Breeschoten1, J. Huisken1, G. Dolmans1, H. de Groot1
1Holst Centre / imec, Eindhoven, The Netherlands
2Panasonic, Osaka, Japan

 

A ULP OOK single-chip transceiver for WBAN applications in 90nm CMOS is presented, operating in the 2.4GHz medical BAN and ISM bands. The TX outputs pulse-shaped OOK with 0dBm peak power, and consumes 2.53mW with 50% OOK. The RX front-end supports up to 5Mb/s with –75dBm sensitivity. Including the digital part, the RX consumes 715μW at 1Mb/s data rate, oversampled at 3MHz.

 

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