Sunday February 14, 2021
On Demand Content will be available on Friday, February 5, 2021, 5:00PM PST
Live Session: Q&A and Discussion: Sunday, February 14, 7:00-9:00 AM PST 30 minute live session = 10 minute summary + 15 minute Q&A + 5 minute break
This course offers and in-depth learning experience on a specific topic. The short course consists of four talks by industry leading experts in a classroom-like format. The short course is targeted at experienced designers who wish to explore a new area in-depth.
PLLs, Clocking, and Clock Distribution
Introduction to PLLs: Phase Noise, Modeling, and Key Wireless Design Considerations
Behzad Razavi, UCLA
PLL Architectures, Tradeoffs, and Key Application Considerations
Woogeun Rhee, Tsinghua University
Clocking, Clock Distribution, and Clock Management in Wireline/Wireless Subsystems
Mozhgan Mansuri, Intel
Processor Clock Generation, Distribution, and Clock Sensor/Management Loops
Phillip Restle, IBM