ANALOG: Circuits with analog-dominated innovation; amplifiers, comparators, oscillators, filters, references; nonlinear analog circuits; digitally-assisted analog circuits; Sensor interface circuits; analog circuits in sub-10nm scaled technologies

DATA CONVERTERS: Nyquist-rate and oversampling A/D and D/A converters; embedded and application-specific A/D and D/A converters; analog to information conversion; time-to-digital converters.

DIGITAL CIRCUITS and ARCHITECTURES & SYSTEMS*: Digital circuits, building blocks, and complete systems (monolithic, 2.5D, and 3D) for microprocessors, micro-controllers, application processors, graphics processors; digital systems for communications, video and multimedia, cryptography, smart cards, security and trusted computing, accelerators, reconfigurable systems, near- and sub-threshold systems, emerging applications. Digital circuits for intra-chip communication, clock distribution, soft-error and variation-tolerant design, power management (i.e. voltage regulators, adaptive digital circuits, digital sensors), PLLs for digital clocking applications, circuit techniques for neuro-computing, and security circuits (i.e. PUFs, TRNGs, side-channel attack countermeasures, and attack-detection sensors).

IMAGERS, MEMS, MEDICAL, & DISPLAYS: Image sensors and SoCs; automotive, LIDAR, and ultrasonic sensors; MEMS sensor systems; wearable, implantable, ingestible electronics, biomedical SoCs, neural interfaces and closed-loop systems; biosensors, microarrays, and lab-on-a-chip; display electronics, displays with sensing functionality; sensing for AR/VR.

MACHINE LEARNING and AI: Chips demonstrating system, architecture and circuit innovations for machine learning and artificial intelligence: processor architectures, accelerators and digital circuits; mixed-signal, analog, near-sensor and in-sensor processing schemes; all architectures and circuits leveraging near-memory and in-memory computation for AI using volatile or non-volatile memories. Hardware optimizations for new ML models including transformers, hyper-dimensional computing, spiking neural networks, etc.

MEMORY: Static, dynamic, and non-volatile memories for stand-alone and embedded applications; memory/SSD controllers; high-bandwidth I/O interfaces; memories based on phase-change, magnetic, spin-transfer-torque, ferroelectric, and resistive materials; array architectures and circuits to improve low-voltage operation, power reduction, reliability, and fault tolerance; application-specific circuit enhancements within the memory subsystem, including in-memory logic functions and compute.

POWER MANAGEMENT: Power management and control circuits, regulators; switched-mode power converter ICs using inductive, capacitive, and hybrid techniques; energy harvesting circuits and systems; wide-bandgap topologies and gate-drivers; power and signal isolators; robust power management circuits for automotive and other harsh environments; circuits for lighting, wireless power and envelope modulators.

RF CIRCUITS and WIRELESS SYSTEMS**: Building blocks and complete solutions at RF, mm-Wave and THz frequencies for receivers, transmitters, frequency synthesizers, transceivers, SoCs, and SiPs. Innovative circuit-level and system-architecture solutions for established wireless standards and future systems or applications such as radar, sensing, and imaging.

TECHNOLOGY DIRECTIONS: Emerging IC and system solutions for: biomedical, sensor interfaces, analog signal processing, power management, computation (including non-CMOS machine learning), data storage, and communication; non-silicon-, carbon-, organic-, metal-oxide-, compound-semiconductor- and new-device-based circuits; nano, flexible, large-area, stretchable, printable, spintronics, quantum, optical, integrated photonics, and 3D-integrated electronics.

WIRELINE: Receivers/transmitters/transceivers for wireline systems, including backplane transceivers, copper-cable links, chip-to-chip communications, 2.5/3D interconnect, on-chip links, optical links, and silicon photonics; exploratory I/O circuits for advancing data rates, bandwidth density, power efficiency, equalization, robustness, adaptation capability, and design methodology; building blocks for wireline transceivers (such as AGCs, analog and ADC/DAC-based front ends, equalizers, clock generation and distribution circuits including PLLs, line drivers, and hybrids).

*This category will be reviewed by either the Digital Circuits or Digital Architecture/Systems subcommittee.
**Papers submitted to this category will be reviewed by either the RF or Wireless Subcommittees.

Firm Deadline for Electronic Submission of Papers:
September 8, 2021 3:00 PM Eastern Daylight Time (19:00 GMT)