Topics of Interest

ISSCC 2017 is soliciting increased participation in the following areas.

Advancements in solid-state circuits and systems continue to propel the ongoing fusion between the physical and virtual worlds. With the resulting growth in sensor deployment, data traffic, and data-center workloads, future systems must employ “intelligent” chips at all levels of the system stack to improve the efficiency at which we acquire, network, store, and process information. Modern applications centered around the Internet of Everything (IoE) and real-time data analytics are driving circuit and system designers toward new ways of leveraging the immense device density and processing power of modern technology. ISSCC 2017 is seeking innovations that will fuel further progress in this development toward a truly smart and interconnected world.

Innovative and original papers are solicited in subject areas including (but not limited to) the following:

ANALOG: Amplifiers, comparators, oscillators, filters, references, regulators, DC-DC converters; power control and management circuits, energy-harvesting circuits; nonlinear analog circuits; digitally-assisted analog circuits.

DATA CONVERTERS: Nyquist-rate and oversampling A/D and D/A converters; time-to-digital converters.

DIGITAL ARCHITECTURES & SYSTEMS: General-purpose microprocessors, micro-controllers, application processors, graphics processors, network processors, digital baseband processors, multi-mode communications systems, video and multimedia, machine-learning/deep-learning systems, neuromorphic systems, cryptographic systems, special function acceleration, systemlevel power management, near-threshold/subthreshold processing for wearable/IoE applications, digital architectures and systems for emerging applications (e.g. virtual reality, artificial intelligence, autonomous vehicles).

DIGITAL CIRCUITS: Building blocks for 2D/3D SoC: including special-purpose digital circuits, intra-chip communication circuits, clock distribution techniques, soft-error and variation-tolerant circuits. Circuits for power management in digital applications: including voltage regulators, adaptive digital circuits, digital sensors; Sub-threshold and Near-threshold circuits; PLLs for digital clocking applications. Circuits for neuro-computing; Hardware security circuits (e.g. PUF).

IMAGERS, MEMS, MEDICAL, & DISPLAYS: Image sensors and companion chips; image-sensor SoCs; MEMS for analog, RF, timing and sensor applications; smart sensors, thermal sensors, ultrasonic sensors; sensor- and transducer-interface circuits; neural interfaces and closed-loop systems; biosensors, microarrays, and lab-on-a-chip; environmental and wearable electronics; biomedical SoCs; display and touch electronics, flexible displays, and displays with integrated sensing functionality.

MEMORY: Static, dynamic, and non-volatile memories for stand-alone and embedded applications; memory/SSD controllers; high-bandwidth I/O interfaces; memories based on phase-change, magnetic, spin-transfer-torque, ferroelectric, and resistive materials; array architectures and circuits to improve low-voltage operation, power reduction, reliability, and fault tolerance; memory subsystem enhancements, including in-memory logic functions.

RF CIRCUITS and WIRELESS SYSTEMS*: Building blocks and complete solutions at RF, mm-Wave, and THz frequencies for receivers, transmitters, frequency synthesizers, transceivers, SoCs, and SiPs. Innovative circuit-level and system architecture solutions for established wireless standards and future systems or applications.

TECHNOLOGY DIRECTIONS: Emerging IC and system solutions for: biomedical, sensor interfaces, analog signal processing, power-management, computation, data storage, security, and communication; non-silicon-, carbon-, organic-, metal-oxide-, compound-, wide-bandgap-semiconductor-, and nano-electronics circuits; flexible, large-area, stretchable, and printable electronics; 3D integration; spintronics; quantum, optical, new-device, and non-transistor-based circuits.

WIRELINE: Receivers/transmitters/transceivers for wireline systems, including backplane transceivers, optical links, chip-to-chip communications, 2.5/3D interconnect, copper cable links, and equalizing on-chip links; exploratory I/O circuits for advancing data rates, power efficiency, and equalization; building blocks for wireline transceivers (such as AGCs, analog and ADC/DAC-based front ends, equalizers, clock generation, and distribution circuits including PLLs, line drivers, and hybrids).

*Papers submitted to this category will be reviewed by either the RF or Wireless Subcommittees.

Firm Deadline for Electronic Submission of Papers:
Monday, September 12, 2016 • 3:00PM Eastern Daylight Time (19:00 GMT)